Volver al ranking

Similares a Using Quartus Prime IP Generator & CORDIC Algorithm: Sine, Cosine & LED Display Output in FPGA

20 vecinos (text_768) · 42 views · Fun with Python · India

Using Quartus Prime IP Generator & CORDIC Algorithm: Sine, Cosine & LED Display Output in FPGA

Fun with Python

@funwithpython8618

42India
14The Discrete Fourier Transform: Most Important Algorithm Ever?

Reducible

@reducible

20.9KEstados Unidos84
8Let’s build a Function Generator for PWM Motor Control #techtok #motorbuilding #experiment

David Malawey

@davidmalawey

6.4KEstados Unidos85
12ESP01 ESP8266 IoT Project | Sinric Pro Alexa & Google Assistant Relay Control 2025

Tech StudyCell

@techstudycell

4.4KIndia84
18Jensen Huang L intelligenza artificiale è una torta a cinque strati. #borsa #AI #nvidia #chip #cina

Startinvesting-it

@startinvesting-it

1.8K84
15FPGA Chaotic Oscillators for Post-Quantum Cryptography

Citedi IPN

@citediipn

281México84
17Improvements in yield and performance of quantum processors and readout systems

Google Quantum AI

@googlequantumai

257Estados Unidos84
7DE1-SoC Tutorial: Connecting HPS to FPGA LEDs with Quartus and Qsys #1

Fun with Python

@funwithpython8618

109India87
13Hardware Implementation and Optimisation of a Chaotic-Chua-Based Pseudo-Random Number Generator

BP International

@bookpublisherinternational

82India84
11ETRI's Revolutionary 8 Qubit Silicon Photonics Quantum Chip

Brains4GoodLife

@brainandlife3036

72Estados Unidos84
2Using Quartus Prime IP Generator & CORDIC Algorithm: Sine & Cosine Calculations in FPGA #3

Fun with Python

@funwithpython8618

33India99
4FPGA Design on Terasic DE1-SoC | 10-bit MSB Counter with LEDs Using Intel Quartus Prime Lite

Fun with Python

@funwithpython8618

30India88
3FPGA Design on Terasic DE1-SoC | 32-bit Counter with LEDs Using Intel Quartus Prime Lite

Fun with Python

@funwithpython8618

23India88
20Exact Synthesis of Qutrit Toffoli+Hadamard and Clifford+T

Institute for Quantum Computing

@quantumiqc

23Canadá84
16Trigonometría Interactiva en Telesecundaria

RED Descartes

@red_descartes

2184
10FPGA Clock Design: Displaying Time on 7-Segment HEX Displays #2

Fun with Python

@funwithpython8618

14India84
5Master FPGA Design: Timing Analysis & Chip Placement for a Karaoke Machine!

Fun with Python

@funwithpython8618

6India87
1Using Quartus Prime IP Generator & CORDIC Algorithm: Sine & Cosine Calculations in FPGA - 7 segment

Fun with Python

@funwithpython8618

4India100
6🚀 FPGA Project: From Gate Design to HDL, Testbench & Timing Analysis! 🔧

Fun with Python

@funwithpython8618

4India87
9Moving Average Display with DE1-SoC: 8-Input Averaging using Push Button & HLS Cyber Workbench

Fun with Python

@funwithpython8618

4India85
19Designing a Half Adder in Verilog | Step-by-Step Guide

Fun with Python

@funwithpython8618

3India84