| ★ | Sobel Edge Detection Using HW/SW Co-Design on SoC FPGA | DE1-SoC FPGA Project | Fun with Python @funwithpython8618 | 53 | India | |
| 16 | Precision in Three Dimensions: Optimizing 3D Hall-Effect Sensing for Rotation and Translation | | 8.6K | — | 86 |
| 18 | Altera extiende SOPORTE FPGAs hasta 2045 | | 1.3K | Perú | 86 |
| 15 | Open Embedded Hardware, nRF52840, and CoffeeCaller — EEI #60 | | 881 | Alemania | 86 |
| 7 | 🎓 Filtros Digitales en dsPIC: Generación de Coeficientes con MATLAB/Simulink y DSP Library | Clase 8 | | 687 | Perú | 87 |
| 6 | Meet the Open-Source Tool That Unlocks FPGA Neural Networks | | 649 | Estados Unidos | 87 |
| 13 | DE1-SoC Tutorial: Connecting HPS to FPGA LEDs with Quartus and Qsys #1 | Fun with Python @funwithpython8618 | 109 | India | 86 |
| 12 | Se completa la primera mitad del Curso Intensivo de Mixed Signal de la UTP | UTPPanama @utppanamaoficial | 93 | Panamá | 86 |
| 17 | Hardware Implementation and Optimisation of a Chaotic-Chua-Based Pseudo-Random Number Generator | BP International @bookpublisherinternational | 82 | India | 86 |
| 20 | Streamlining Structural Test with Keysight by Salvador Galvan | | 79 | México | 86 |
| 11 | El Ecosistema de Hardware para IA: Video y Presentación Comparativa (GPU, NPU, TPU y FPGA) | Tomás GD | Live Coding • Linux • Apps • Devlogs @tomasgd | 76 | España | 86 |
| 19 | LOCA series: TuRTLe: Artificial Intelligence for Chip Design research at BSC | | 73 | España | 86 |
| 1 | Implementing Sobel Edge Detection with HLS Directives: Area vs. Performance Trade-offs | Fun with Python @funwithpython8618 | 64 | India | 94 |
| 2 | Exploration of a HW/SW FPGA-based Co-Design of a Visual SLAM Algorithm | Bhavay Arora | | 58 | Alemania | 88 |
| 5 | Creating a VGA Interface with DE1-SoC FPGA: Blue Square on Yellow Background #5 | Fun with Python @funwithpython8618 | 47 | India | 88 |
| 9 | FPGA Design on Terasic DE1-SoC | 10-bit MSB Counter with LEDs Using Intel Quartus Prime Lite | Fun with Python @funwithpython8618 | 30 | India | 86 |
| 10 | Energy Efficient On Chip Adaptive Spike Sorting And Multiresolution DWT Via Reconfigurable MAC And C | Computer Science & IT Conference Proceedings @computerscienceitconferenc7375 | 30 | Australia | 86 |
| 8 | FPGA Design on Terasic DE1-SoC | 32-bit Counter with LEDs Using Intel Quartus Prime Lite | Fun with Python @funwithpython8618 | 23 | India | 86 |
| 14 | What Are The Key Milestones In D-Wave Processor Development? | Quantum Tech Explained @quantumtechexplained | 21 | Estados Unidos | 86 |
| 3 | Moving Average Display with DE1-SoC: 8-Input Averaging using Push Button & HLS Cyber Workbench | Fun with Python @funwithpython8618 | 4 | India | 88 |
| 4 | 🚀 FPGA Project: From Gate Design to HDL, Testbench & Timing Analysis! 🔧 | Fun with Python @funwithpython8618 | 4 | India | 88 |